Sep 14 – 16, 2022
IIA Bangalore
Asia/Kolkata timezone
Poster Size for META 2022 : A0 Size Poster is preferred as fixing board size at IIA is 56 inches x 46 inches (landscape orientation)

Multi-Element Correlator & Beamformer using OpenCL on FPGA Accelerator Card

Not scheduled
20m
IIA Bangalore

IIA Bangalore

Speaker

Raghuttam Hombal (Savitribai Phule Pune University)

Description

Radio Interferometry refers to the process of combining signals from multiple antennas to form an image of the radio source in the sky. Radio-astronomical signal processing using array telescopes is computationally challenging and poses strict performance and energy-efficiency requirements. The GMRT is one of the largest arrays with many antennas working in the metre wavelength. The ongoing developmental activities for expansion of the GMRT (called eGMRT) demand a many fold increase in the computational cost and power budget while providing an increased collecting area as well as field-of-view by building more antennas each equipped with phased array feed (PAF). Recent FPGAs provide higher Flops per Watt making it an energy-efficient hardware platform suitable for projects like the eGMRT requiring a high compute-to-power ratio. However, the traditional programming model for FPGAs is a primary drawback of using FPGAs for high-performance computing. Aided by the recent advancement of parallel programming on FPGAs using Open Computing Language (OpenCL), allows FPGAs to be used as general purpose accelerators like GPUs. The aim of this project is to design an energy-efficient multi-element correlator and beamformer on an FPGA Accelerator Card using OpenCL and to explore the possibilities of using such systems for real-time, number-crunching tasks.

To demonstrate this, we have developed a two-element interferometer and beamformer on an Intel's Arria-10 FPGA Accelerator Card using OpenCL. Digital signal processing modules used in radio telescopes like Fast Fourier Transform, Delay Correction, Fringe Stop, Correlation and Beamforming (Incoherent Array, IA as well as Phased Array, PA) are implemented using parallel processing techniques. The design supports real-time processing of 400MHz bandwidth. An offline 2-element, 100MHz bandwidth, 4096 points correlator providing 1.34s visibilities and 163.84 mico-sec beams (IA and/or PA) are implemented on the FPGA Accelerator card. The developments of this system as well as the results from processing recorded baseband data of calibrator and pulsar will be presented along with highlighting the comparison with the outputs from the GMRT Wideband Back-end (GWB) system. This project demonstrates a rapid development cycle of building a high-performance, energy-efficient system using low-power devices like FPGAs.

Presentation type Oral

Primary authors

Raghuttam Hombal (Savitribai Phule Pune University) Mekhala Muley (GMRT, NCRA-TIFR)

Co-authors

Mr Harshvardhan S Reddy (GMRT, NCRA-TIFR) Mr Sanjay S Kudale (GMRT, NCRA-TIFR) Dr Jayanta Roy (GMRT, NCRA-TIFR)

Presentation materials

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